Pre-Silicon Verification Engineer

ASIC Verification Engineer Mid-level (L4 equivalent) 2-5 years

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Apple

NVIDIA

Qualcomm

AMD

Broadcom

Marvell

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The job description

Tech stack. SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, SVA, regression farm (LSF/Grid), gate-level simulation, SDF annotation, Python

About the role

You will own the simulation-based verification effort that stands between RTL and tapeout at a fabless semiconductor company. Pre-silicon verification is where bugs are cheapest to fix, and this role carries that responsibility: building the regressions, managing the signoff gates, and driving coverage and bug closure to the point where the team can confidently freeze RTL. Your regressions are the heartbeat of the project, running nightly across thousands of tests and giving every stakeholder a daily read on design health. You will decide which failures matter, which coverage holes are real risk, and when the design has earned its tapeout. The discipline you bring to regression management and signoff rigor is what lets the company tape out on schedule with confidence instead of hope.

What you will achieve

Build and maintain the project regression suite, scaling it to 5,000-plus tests with pass rates above 98 percent and same-day triage of every failure.
Drive the pre-tapeout signoff process: functional coverage, code coverage, and assertion coverage all closed to plan targets before each RTL freeze milestone.
Reduce regression runtime by 35 percent through suite optimization, test selection, and parallelization across the compute farm.
Catch and drive closure on at least 95 percent of RTL bugs found in simulation before they can reach gate-level or post-silicon stages.
Deliver gate-level simulation signoff with SDF annotation, confirming timing-clean behavior on critical paths ahead of tapeout.

What you will bring

Must-haves

2 to 5 years of pre-silicon verification experience with SystemVerilog and UVM on production RTL.
Deep experience managing large regression suites: scheduling, triage workflows, and failure bucketing at scale.
Strong understanding of coverage-driven signoff: functional, code, and assertion coverage metrics and how they gate milestones.
Hands-on SVA for simulation checkers and protocol compliance monitoring.
Experience debugging across RTL and gate-level simulations, including SDF-annotated runs.
Scripting skills in Python, Perl, or Tcl for regression automation and farm job management.
Familiarity with coverage merging, exclusion reviews, and waiver discipline.

Nice-to-haves

Experience with low-power simulation using UPF power intent.
Exposure to CDC and RDC verification flows as pre-silicon signoff items.
Knowledge of fault simulation or safety-related verification metrics.
Familiarity with emulation for accelerating long regressions.