Power/Performance CPU Architect

About the role

You will work at the intersection of power and performance at a semiconductor company, architecting the techniques that let processors deliver maximum performance within strict power and thermal limits. This is the discipline behind every modern processor's ability to burst far beyond its nominal TDP for short periods and to sip power when idle: dynamic voltage and frequency scaling, power gating, clock gating, adaptive policies, and the telemetry and control loops that orchestrate them. You will model power and performance together, define the control architecture, and prove that the processor meets its efficiency commitments.

What you will achieve

• Define the power management architecture for a CPU program including DVFS domains, power gating strategy, idle state definitions, and the hardware-software interfaces that control them.
• Build integrated power-performance models that predict both benchmark scores and energy consumption, enabling the program to optimize for performance per watt rather than performance alone.
• Design adaptive control policies such as workload-aware frequency selection, thermal management responses, and race-to-halt strategies, validated through modeling across diverse workloads.
• Specify the telemetry architecture including power sensors, activity monitors, and performance counters that the power controller and software depend on for decisions.
• Drive the PPA tradeoff process with combined power-performance data, ensuring architecture decisions account for the full energy cost rather than performance in isolation.
• Validate power and performance targets on silicon, correlating measurements against models and refining both the design and the methodology for future programs.

What you will bring

Must-haves

• 5 to 8 years of experience in CPU power management architecture, power modeling, or performance-per-watt optimization with shipped products.
• Strong understanding of DVFS, power gating, clock gating, retention, and idle state architectures and their hardware-software interfaces.
• Experience with power modeling methodologies from architectural-level estimation through correlation with silicon measurements.
• Knowledge of thermal constraints and how they shape sustained versus burst performance behavior.
• Performance modeling skills sufficient to evaluate power policies against their performance impact honestly.
• Familiarity with firmware or hardware power controller design and the control theory basics behind stable, responsive policies.
• Data-driven decision making with careful attention to measurement methodology and the limits of models.

Nice-to-haves

• Experience with advanced techniques such as adaptive voltage scaling, in-situ monitors, or ML-based power policies.
• Knowledge of package and system-level power delivery constraints.
• Background in mobile or datacenter efficiency optimization at scale.