Post-Silicon Verification Engineer

About the role

You will join a semiconductor company where post-silicon verification proves that the chip coming back from the fab actually works as designed. This role lives in the lab: bringing up first silicon, running characterization and ATE test programs, and debugging the issues that simulation never caught. When pre-silicon verification says the design is clean and the lab disagrees, you are the engineer who finds out why, working shoulder to shoulder with design, DFT, and product engineering until each issue is root-caused. You will develop the instincts that only silicon teaches: reading shmoo plots, correlating marginal behavior with design intent, and distinguishing a test artifact from a genuine bug. Your escape analysis closes the loop back to pre-silicon, making every project you touch better than the last.

What you will achieve

• Bring up first silicon to functional boot within two weeks of packaged parts arriving, establishing the lab baseline for the whole project.
• Develop and execute silicon characterization plans covering voltage, frequency, and temperature corners, producing shmoo plots that define the operating envelope.
• Root-cause post-silicon failures to RTL bugs, testbench escapes, or physical issues, closing at least 90 percent of assigned silicon issues with confirmed fixes or workarounds.
• Correlate pre-silicon predictions with silicon measurements, feeding escape analysis back to the verification team so the next project catches similar bugs in simulation.
• Support ATE test program bring-up and debug, improving first-pass production test yield on new silicon revisions.

What you will bring

Must-haves

• 2 to 5 years of post-silicon validation, silicon debug, or product engineering experience on complex SoCs or ASICs.
• Hands-on lab skills: oscilloscopes, logic analyzers, JTAG debuggers, and board-level bring-up of new silicon.
• Experience with ATE platforms such as Advantest 93K or Teradyne UltraFLEX, including test program debug.
• Ability to read RTL and simulation waveforms to connect silicon misbehavior back to design intent.
• Scripting in Python or C for lab automation, data collection, and failure analysis.
• Understanding of DFT structures (scan, MBIST, boundary scan) and how to use them for silicon debug.
• Clear documentation habits for silicon issue tracking, errata, and characterization reports.

Nice-to-haves

• Pre-silicon verification background that helps trace escapes back to testbench gaps.
• Experience with high-speed interface bring-up such as PCIe, DDR, or SerDes links.
• Familiarity with failure analysis techniques including emission microscopy or FIB.
• Experience with silicon debug automation and data analytics.