Post-Silicon Design Validation Engineer

About the role

You will validate real silicon in the lab at a semiconductor company, proving that the chip on the bench matches the design that taped out. You will write validation plans with the designers, bring up first silicon, and debug the failures that only appear at speed, at voltage corners, and under thermal stress. When you find a silicon bug, you close the loop with the design team on root cause and feed the lesson back into pre-silicon verification so it never escapes again.

What you will achieve

• Deliver silicon bring-up on first samples, achieving basic boot and functional operation within two weeks of receiving packaged parts.
• Drive validation plan execution to 100 percent of planned coverage across functional, electrical, and system-level tests for your assigned blocks.
• Ship root-cause analysis on every silicon issue found, distinguishing design bugs from test-setup artifacts and documenting the fix or workaround with evidence.
• Cut validation cycle time by automating lab measurements and test sequencing in Python, targeting 3x throughput on repetitive characterization runs.
• Reduce future escapes by writing pre-silicon verification feedback for each silicon bug: the exact test that would have caught it before tapeout, handed to the DV team.

What you will bring

Must-haves

• 2 to 5 years of experience in post-silicon validation, silicon debug, or closely related lab-based hardware work.
• Hands-on skill with lab equipment: oscilloscopes, logic analyzers, power supplies, and JTAG-based debug tools, used daily and confidently.
• Ability to read schematics, board layouts, and datasheets to design valid, well-grounded test setups.
• Working knowledge of digital design and common interfaces (I2C, SPI, UART, PCIe, or DDR) at the signal level, not just the protocol level.
• Structured debug discipline: hypothesis, isolation, reproduction, and clear documentation of findings that others can follow.
• Collaborative mindset for working with designers, DFT engineers, and product engineers on failure analysis without blame.
• Comfort with ambiguity: first silicon never behaves exactly as expected, and you narrow the unknown systematically.

Nice-to-haves

• Experience with ATE or production test correlation.
• Familiarity with thermal and voltage-margin testing methodologies.
• Programming skills for instrument control (SCPI, VISA) beyond basic scripting.
• Exposure to failure analysis techniques (emission microscopy, laser probing) or FIB workflows.