Photolithography Process Engineer

Semiconductor Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. scanners/steppers, overlay control, OPC, EUV/DUV, resist processing, CD control, focus-exposure matrices, reticle management, APC

About the role

A wafer fab needs a lithography process engineer to own patterning performance on scanner and stepper tools, the most capital-intensive and technically demanding step in the fab. You will control critical dimension, overlay, and defectivity for the most demanding layers in the flow, where nanometer errors become dead chips. Every chip starts with your patterns, and the resolution limits you manage define what the technology node can actually build, making lithography the pacemaker of the entire fab, and your ownership keeps it running.

What you will achieve

Deliver overlay performance within 20 percent of tool specification on all critical layers through recipe tuning, APC feedback, alignment strategy optimization, and lot-to-lot overlay learning.
Reduce CD variation across wafer and lot by 15 percent with optimized focus-exposure control, dose mapping, resist process stability, and chuck flatness compensation.
Drive defect reduction on patterning steps, cutting litho-induced inline defects by 25 percent through track process improvements, scanner contamination control, and optimized develop and rinse processes.
Own reticle lifecycle management including inspection, cleaning, and retirement criteria, so reticle-related rework stays below 1 percent of starts, with pellicle integrity monitored on every critical reticle.
Cut scanner qualification time after maintenance by 30 percent with streamlined verification recipes that prove tool health without wasting production capacity, getting scanners back to production lots faster and recovering lost capacity.

What you will bring

Must-haves

BS or MS in optics, physics, electrical engineering, chemical engineering, or materials science.
2 to 5 years in photolithography process engineering or a closely related patterning role in a production fab.
Hands-on experience with DUV or EUV scanners, or advanced steppers, including recipe setup, troubleshooting, first-level tool recovery, and escalation to equipment engineering when needed.
Understanding of OPC concepts and resolution enhancement techniques such as off-axis illumination and phase-shift masks.
Experience with overlay and CD metrology and control strategies, including sampling plans and feedback loops.
Ability to work flexible schedules during critical layer processing, tool installs, or excursion recovery.

Nice-to-haves

EUV-specific experience covering source, mask, and pellicle handling challenges.
Computational lithography or lithography simulation background for process window analysis.
Experience with multi-patterning schemes such as SADP/SAQP or LELE.