Networking Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog/UVM, Ethernet/PCIe protocol verification, packet-level testbenches, traffic generators, SerDes-adjacent digital logic, P4 or forwarding concepts

About the role

You will verify networking silicon at a semiconductor company building switch, NIC, or DPU chips where a single dropped packet at line rate is a product failure. Working with packet-processing designers, you will prove that forwarding pipelines classify, modify, and switch packets correctly at full throughput under adversarial traffic. Your verification stands between the design and the data center, and your traffic generators are meaner than any real network. In networking silicon, correctness at line rate is the entire product: a chip that forwards correctly at half speed is a failed chip, and your signoff is what lets the company promise full performance.

What you will achieve

Deliver packet-level UVM testbenches with constrained-random traffic generation covering protocol corner cases (jumbo frames, errors, back-to-back bursts, congestion collapse).
Drive line-rate performance verification proving sustained throughput and bounded latency under worst-case traffic mixes defined with architects.
Ship protocol compliance checkers for Ethernet, PCIe, or equivalent interfaces, validated against VIP and directed compliance suites at 100 percent.
Cut debug time on packet-loss or misordering bugs by building per-packet tracing from ingress to egress through the entire pipeline.
Reduce field risk by verifying error handling and resilience: link flaps, CRC errors, buffer exhaustion, and failover scenarios, designed together with the designers.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience, ideally with networking, packet processing, or high-speed interface designs.
Strong SystemVerilog/UVM skills with experience building packet-based testbenches and scoreboards that track thousands of in-flight packets.
Deep knowledge of at least one networking protocol (Ethernet MAC/PCS, PCIe, or InfiniBand) including its error and flow-control mechanisms.
Understanding of pipeline architectures: parsing, lookup, queuing, scheduling, and traffic management.
Experience with performance and throughput verification, not just functional correctness: you measure, you do not assume.
Ability to work with designers on the verification implications of pipeline microarchitecture and buffer sizing.
Adversarial mindset: you generate the traffic the designers hoped would never arrive.

Nice-to-haves

Familiarity with P4 or programmable pipeline concepts.
Experience with formal verification of arbiters, schedulers, or flow-control logic.
Knowledge of time-sensitive networking, RDMA, or congestion-control protocols.
Exposure to system-level testing with real traffic generators or network testers.