Mixed Signal IC Design Engineer

Mixed Signal Design Engineer Mid-level (L4 equivalent) 2-5 years

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Texas Instruments

Analog Devices

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Marvell

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The job description

Tech stack. Cadence Virtuoso, Spectre, Calibre DRC/LVS/PEX, EMX, Virtuoso Layout, foundry PDKs (28nm and below)

About the role

You will be a silicon implementation specialist at a fabless semiconductor company, taking analog schematics and turning them into tapeout-clean layout that performs as simulated. The team separates architecture from implementation deliberately: your craft is floorplanning, matching, routing, and parasitic control that preserve circuit intent down to the last femtofarad. This role matters because the difference between a good schematic and good silicon is layout, and you own that difference. You will sit with the circuit designers daily, and your layout judgment will be trusted as a design input rather than treated as a downstream service.

What you will achieve

Deliver tapeout-clean analog layouts for two to three blocks per year (ADCs, PLLs, amplifiers, or references) with zero DRC/LVS violations and parasitic extraction that matches schematic intent within the designer's budget.
Reduce performance loss from layout by owning floorplan and routing strategy: critical matching, symmetry, shielding, and reference routing that keep post-layout simulation within 10% of schematic on key specs.
Cut layout iteration cycles by doing first-pass layout reviews yourself: catching well proximity effects, antenna violations, and density issues before the formal Calibre runs.
Drive EM/IR-clean power routing for analog blocks, sizing power grids against peak current with margin and verifying with EM analysis before sign-off.
Improve analog isolation at the block level through guard rings, deep n-well strategy, and substrate contact discipline that you specify and verify.

What you will bring

Must-haves

2-5 years doing analog/mixed-signal IC layout or design-for-layout in CMOS, with tapeouts on your record.
Expert Virtuoso Layout skills: matching structures, common-centroid, interdigitation, shielding, and clean analog floorplanning.
Deep understanding of layout parasitics: capacitance, resistance, coupling, and how they degrade noise, bandwidth, and matching.
Fluency in Calibre DRC/LVS/PEX and the ability to debug violations to root cause quickly.
Knowledge of latch-up, antenna, ESD, and density rules and how to satisfy them without breaking circuit intent.
Ability to work closely with circuit designers: reading schematics, understanding what matters electrically, and pushing back when a layout request hurts performance.

Nice-to-haves

Experience with EMX or similar EM extraction for critical passives and inductors.
FinFET layout experience with layout-dependent effects (LOD, WPE) awareness.
SKILL scripting for layout automation and parameterized cells.