Microarchitect

About the role

You will work as a microarchitect at a semiconductor company, designing the internal structure of processor pipelines at the level of queues, arbiters, state machines, and control logic. Where architects decide what the processor should do, microarchitects decide precisely how it does it: the depth of each queue, the policy of each arbiter, the timing of each handshake, and the exact behavior of every corner case. Your models and specifications become the blueprint the RTL team implements, and the quality of your microarchitecture determines whether the design meets its frequency, area, and performance targets.

What you will achieve

• Develop detailed microarchitecture designs for pipeline stages or functional units, specifying queue depths, arbitration policies, bypass networks, and control flow with enough precision for direct RTL implementation.
• Build cycle-accurate or cycle-approximate models of your blocks that predict throughput, latency, and resource utilization, and use them to size structures optimally rather than by guesswork or copying prior designs.
• Optimize your microarchitecture for the target frequency by understanding critical paths, proposing pipeline cuts or restructuring where timing demands it, and quantifying the performance cost of every timing-driven change.
• Write microarchitecture specifications that capture every state, transition, interface protocol, and corner case, eliminating ambiguity that would otherwise surface as bugs months later in verification.
• Support the RTL design team through implementation, answering questions quickly, reviewing code for fidelity to the specification, and updating the specification cleanly when implementation realities require changes.
• Analyze performance counter data and simulation results to identify microarchitectural bottlenecks in your blocks, then propose and validate targeted improvements with measured gains.

What you will bring

Must-haves

• 2 to 5 years of experience in processor microarchitecture, CPU RTL design, or performance modeling with real product exposure.
• Strong understanding of pipelining, out-of-order execution, speculation, and the classic hazards and their resolutions.
• Ability to reason quantitatively about queues, arbitration, backpressure, and throughput using both models and analytical methods.
• Fluency in SystemVerilog sufficient to review RTL against a specification and to prototype microarchitectural ideas.
• Familiarity with timing closure concepts and how microarchitectural choices affect achievable frequency and area.
• Clear, precise technical writing for specifications that implementation teams depend on.
• Detail orientation combined with pragmatism: you sweat the corner cases that matter and simplify the ones that do not.

Nice-to-haves

• Experience with formal verification of control logic or protocol properties.
• Knowledge of low-power microarchitecture techniques such as clock gating, operand isolation, and power-aware scheduling.
• Background in cache or memory subsystem microarchitecture.