Low Power IC Design Engineer

About the role

You will join an ultra-low-power semiconductor company designing chips that run for years on coin cells or harvested energy. The team builds sensor nodes, wearables, and IoT endpoints where every nanoamp is budgeted and sleep current decides the product's market life. This role matters because battery life is the product spec customers quote: your circuits are the reason a device lasts five years instead of two. Energy harvesting and decade-long deployments keep pushing the power floor lower every generation. Field deployments number in the millions, so small power wins compound enormously. You will also architect the power-mode state machine that duty-cycles every block, since sleep-to-active transition energy often dominates the budget in real deployments.

What you will achieve

• Ship products with class-leading sleep and active power, hitting sub-microamp standby targets on first silicon
• Design subthreshold and near-threshold circuits that hold functionality and yield across process variation at ultra-low supplies
• Cut active energy per task through duty cycling, aggressive power gating, and event-driven architectures co-designed with the digital team
• Deliver always-on domains (wake-up receivers, timers, sensor monitors) that sip power while never missing their trigger events
• Drive power-state verification across all modes and transitions, eliminating leakage paths and sequencing bugs before tapeout
• Own silicon power correlation, measuring real current profiles in the lab and feeding discrepancies back into models and budgets
• Benchmark competitor power numbers publicly and privately, keeping the product story best-in-class

What you will bring

Must-haves

• 2-5 years designing ultra-low-power analog or mixed-signal circuits with shipped battery-powered products
• Deep understanding of leakage mechanisms and low-power techniques: power gating, body biasing, multi-Vt design, and retention strategies
• Experience designing in subthreshold or near-threshold regimes, including variation-tolerant biasing and startup circuits
• Fluency in Cadence Virtuoso and Spectre for low-current simulation, including the convergence care picoamp circuits demand
• Strong power-budgeting discipline: you can account for every nanoamp in a sleep state and defend each one
• Familiarity with energy harvesting or wireless power interfaces and their circuit implications
• B.S. or M.S. in Electrical Engineering with a low-power circuits focus

Nice-to-haves

• Experience with on-chip power management: nano-amp LDOs, switched-capacitor converters, or charge pumps
• Familiarity with Bluetooth LE, LoRa, or other low-power wireless PHY constraints
• Prior work on medical implants or devices with decade-scale lifetime requirements