Low Power CPU Design Engineer

About the role

You will design power-efficient CPU logic at a semiconductor company, applying low-power techniques throughout the RTL design process to minimize energy consumption without compromising performance. Low-power designers make energy efficiency a first-class design goal rather than an afterthought: they gate clocks aggressively, isolate operands intelligently, partition power domains thoughtfully, and verify that power intent is implemented correctly at every stage. Your work extends battery life in mobile products, enables fanless client designs, and reduces operating costs in datacenters.

What you will achieve

• Implement CPU blocks with power-efficient RTL practices including aggressive clock gating, operand isolation, data-dependent gating, and activity-aware design, measuring savings rigorously with power analysis tools.
• Write and maintain complete UPF power intent for your blocks, specifying power domains, isolation cells, retention registers, level shifters, and power switch controls correctly and completely.
• Verify low-power behavior through power-aware simulation, checking power state transitions, isolation values, retention restore, and reset behavior across every operating mode.
• Analyze power consumption of your blocks across representative workloads, identifying the dominant contributors through careful measurement and targeting optimization where it genuinely matters.
• Collaborate with physical design engineers on the implementation of power structures including power switch placement, isolation cell insertion, and always-on routing integrity.
• Support silicon power correlation, comparing measured power against pre-silicon estimates across workloads and operating points, and improving estimation accuracy for future designs.

What you will bring

Must-haves

• 2 to 5 years of experience in digital design with significant low-power design exposure and tapeout experience.
• Strong knowledge of low-power techniques: clock gating, power gating, multi-threshold voltages, DVFS interfaces, retention, and isolation strategies.
• Experience with UPF power intent specification and low-power implementation and verification flows.
• SystemVerilog design skills with power-aware coding discipline applied consistently.
• Familiarity with power analysis and estimation tools and methodologies from RTL through sign-off.
• Understanding of power-aware verification including state transition coverage and isolation checking.
• Measurement-driven approach: you quantify power impact with data rather than assuming savings from techniques.

Nice-to-haves

• Experience with advanced process nodes where leakage power optimization is critical.
• Knowledge of system-level power management architectures and firmware interfaces.
• Familiarity with thermal-aware design considerations and dynamic thermal management.
• Exposure to power modeling for architectural exploration.