Layout-Aware IC Design Engineer

About the role

You will join a precision analog company as a layout-aware IC design engineer, the designer who treats layout as a first-class design variable rather than an afterthought. The team builds high-performance analog where parasitics, matching, and coupling decide whether simulation survives contact with silicon. This role matters because the gap between schematic and silicon is where tapeouts fail: you close that gap by designing with the physical implementation in mind from day one. As processes shrink, the schematic-to-silicon gap widens, and your skill set grows more valuable every node.

What you will achieve

• Deliver blocks whose post-layout simulation matches schematic performance within tight margins, eliminating parasitic-driven re-spins
• Design floorplans and routing strategies that control coupling, IR drop, and thermal gradients before extraction ever runs
• Cut layout iterations by writing precise matching, shielding, and routing constraints that layout engineers can execute correctly the first time
• Drive parasitic-aware design methodology: early extraction, EM modeling of critical nets, and signoff criteria the whole team adopts
• Own the correlation between extracted simulation and silicon measurement, identifying which parasitics actually matter for each circuit class
• Mentor schematic-focused designers on layout effects, raising the team's first-pass layout success rate measurably
• Develop internal training on parasitic-aware design that shortens the learning curve for new analog hires

What you will bring

Must-haves

• 2-5 years of analog IC design with deep layout involvement: you have drawn or directly driven critical analog layout yourself
• Strong understanding of parasitic effects: capacitance, resistance, coupling, and substrate noise, and how each degrades specific circuits
• Mastery of matching techniques: common-centroid, interdigitation, dummy devices, and gradient cancellation for precision circuits
• Proficiency in Cadence Virtuoso, Calibre (DRC/LVS), and parasitic extraction flows through post-layout Spectre simulation
• Experience with EM simulation of critical interconnect and the judgment to apply it where it changes design decisions
• Familiarity with floorplanning for noise isolation: guard rings, deep n-well, separate supplies, and sensitive-node shielding
• B.S. or M.S. in Electrical Engineering with an analog IC design focus

Nice-to-haves

• Direct experience as a layout designer earlier in your career, or formal layout training
• Familiarity with automated analog layout tools and their limitations
• Prior work on high-voltage or high-current layout where EM and thermal rules dominate