Interconnect Architect

About the role

You will architect the on-chip interconnect at a semiconductor company, designing the network that carries every byte between cores, caches, memory controllers, and IO. Interconnect architects determine the topology, routing, arbitration, coherency transport, and quality-of-service policies of the chip's nervous system, and their decisions bound the scalability, latency, and bandwidth of the entire product. You will model traffic extensively, specify protocols precisely, and prove the network correct and performant under the worst cases the system can produce.

What you will achieve

• Define the interconnect topology for a CPU or SoC program, selecting among mesh, ring, crossbar, or hierarchical options through quantitative analysis of latency, bandwidth, power, area, and scalability.
• Architect the coherency transport including message classes, virtual channels, ordering rules, and deadlock avoidance, producing specifications rigorous enough for implementation and formal verification.
• Design quality-of-service and arbitration schemes that guarantee bandwidth and latency for critical traffic classes while maintaining high utilization under mixed workloads.
• Model interconnect performance under synthetic stress patterns and real application traces, identifying congestion points and validating that the network meets its targets with margin.
• Partner with physical design on floorplan-aware topology decisions, balancing the ideal logical network against wiring realities, repeater costs, and timing constraints.
• Validate the interconnect on silicon through performance counter analysis and stress testing, confirming bandwidth, latency, and fairness targets are met in production configurations.

What you will bring

Must-haves

• 5 to 8 years of experience in interconnect, network-on-chip, or fabric architecture with shipped silicon.
• Deep understanding of interconnect topologies, routing algorithms, flow control, arbitration, and their performance implications.
• Knowledge of cache coherency protocols and how they map onto interconnect message classes and ordering requirements.
• Experience with deadlock, livelock, and protocol-level correctness analysis for on-chip networks.
• Performance modeling skills for evaluating networks under diverse traffic patterns.
• Ability to write precise protocol and microarchitecture specifications for interconnect components.
• Familiarity with the physical design implications of interconnect topology including wiring, repeaters, and floorplanning.

Nice-to-haves

• Experience with chiplet-to-chiplet interconnects such as UCIe or proprietary die-to-die links.
• Knowledge of emerging standards for coherent device attachment such as CXL.
• Background in formal verification of interconnect protocols.