Imaging/Sensor Mixed Signal Engineer

About the role

You will design readout and signal-chain circuits for image sensors at a fabless semiconductor company building CMOS image sensors for mobile, automotive, and industrial markets. The team owns the pixel array interface: column readout, ADCs, CDS, and the timing that turns photons into digital images. This role matters because read noise, dynamic range, and frame rate are set by your readout chain, and they decide whether the sensor wins the socket. You will work with pixel designers and the digital imaging pipeline team, since readout noise, timing, and image processing form one chain your circuits anchor.

What you will achieve

• Ship sensor readout blocks (column ADCs, programmable gain amplifiers, CDS circuits, or row drivers) with measured read noise and dynamic range meeting the sensor spec on first silicon.
• Drive read noise down through circuit technique: correlated double sampling, chopper stabilization, and column-level noise budgeting that push input-referred noise toward the single-electron regime where targeted.
• Reduce column fixed-pattern noise by designing offset and gain calibration (per-column trimming, digital correction) that holds FPN below the visible threshold across temperature.
• Own the high-speed readout path: column-parallel ADC timing, ramp generation, and data serialization that sustain the target frame rate without row-time violations.
• Cut sensor bring-up time by writing characterization plans: photon transfer curves, dark current measurement, and linearity analysis executed with the validation team on first silicon.

What you will bring

Must-haves

• 2-5 years designing image sensor readout or sensor interface circuits (column ADCs, PGAs, CDS, or ROIC) with tapeout and measured noise results.
• Deep understanding of image sensor metrics: read noise, dynamic range, full-well capacity, dark current, PRNU/DSNU, and how readout circuits affect each.
• Experience with column-parallel ADC architectures (single-slope, SAR, or cyclic) and the tradeoffs of speed, power, and noise per column.
• Knowledge of pixel operation: 4T pixels, transfer gates, floating diffusion, and the timing sequences that drive them.
• Correlated double sampling and other kTC noise cancellation techniques, designed at the transistor level.
• Lab skills for sensor characterization: photon transfer curves, noise measurement, and optical test setups.

Nice-to-haves

• Experience with stacked (3D) image sensors and pixel-to-logic interconnect.
• Knowledge of HDR techniques (dual conversion gain, lateral overflow, multi-exposure).
• Familiarity with MIPI CSI-2 or other sensor output interfaces.