Floating Point Unit (FPU) Design Engineer

CPU Design Engineer Senior (L5 equivalent) 5-8 years

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The job description

Tech stack. Floating-point unit design, IEEE 754 compliance, SystemVerilog, computer arithmetic, FP verification methodology, PPA optimization, Python, reference modeling

About the role

You will design floating-point units for CPUs at a semiconductor company, implementing the fused multiply-add datapaths, adders, multipliers, dividers, and conversion units that power scientific computing, graphics, and AI workloads. FPU designers work in a domain where correctness is defined by an exacting international standard: every operation must match IEEE 754 semantics precisely, including rounding modes, exception flags, and denormal handling across all supported precisions. Your units must be simultaneously bit-exact, high-throughput, and efficient.

What you will achieve

Design floating-point execution datapaths including fused multiply-add units, adders, multipliers, dividers, and format converters, achieving IEEE 754 compliance across all supported precisions and rounding modes.
Implement correct handling of every FP special case: NaNs with payload propagation, infinities, denormal inputs and outputs, underflow, overflow, and inexact results, with proper exception flag generation.
Optimize FP datapaths for the target frequency through careful pipeline design, arithmetic algorithm selection, and stage balancing, trading latency against throughput based on the core's requirements.
Verify FP correctness exhaustively using directed corner-case tests, constrained-random testing against bit-accurate reference models, and formal methods for critical rounding properties.
Drive PPA optimization for the FPU, which ranks among the largest and most power-hungry blocks in the core, without compromising compliance, throughput, or frequency targets.
Support silicon validation of FP behavior and performance, confirming standard compliance on hardware and characterizing real workload throughput against projections.

What you will bring

Must-haves

5 to 8 years of experience in floating-point, complex datapath, or high-performance arithmetic design with shipped products.
Deep knowledge of IEEE 754 semantics including rounding modes, exception handling, and special value behavior.
Strong computer arithmetic background: FMA algorithms, division and square root iteration methods, and their timing, power, and area tradeoffs.
Expert SystemVerilog design skills for wide, timing-critical datapaths with complex control.
Rigorous verification discipline appropriate for a domain where a single incorrect result in a billion operations is unacceptable.
Experience with reference modeling, differential testing, and FP-specific verification methodologies.
Patience and meticulousness for the exhaustive corner-case work this domain demands.

Nice-to-haves

Experience with emerging FP formats such as bfloat16, FP8 variants, or other ML-oriented precisions.
Knowledge of formal verification techniques applied to floating-point correctness proofs.
Background in GPU, accelerator, or HPC floating-point design.
Familiarity with elementary function approximation hardware such as divide and square root units.