Datapath Design Engineer

About the role

You will design processor datapaths at a semiconductor company, implementing the arithmetic units, register files, bypass networks, and data movement structures at the heart of CPU execution. Datapath designers work where timing is tightest and every picosecond counts: adders, multipliers, shifters, and the forwarding networks that feed them must meet aggressive frequency targets while staying within power and area budgets. Your designs determine the raw execution throughput of the processor, and your optimization skill shows up directly in the product's competitive positioning.

What you will achieve

• Design high-performance datapath blocks such as ALUs, multipliers, dividers, shifters, and multi-ported register files, meeting aggressive timing targets through skilled circuit-aware RTL design.
• Optimize arithmetic implementations for the target frequency, selecting algorithms and structures such as carry-lookahead adders, Wallace tree multipliers, or Booth encoding based on quantitative timing, power, and area analysis.
• Design bypass and forwarding networks that minimize operand delivery latency across the pipeline, working closely with pipeline architects on the allocation of the timing budget.
• Drive PPA optimization for your blocks relentlessly, trading off structural choices against synthesis and physical design feedback to land the best overall result rather than optimizing any single metric in isolation.
• Verify datapath functionality exhaustively including arithmetic corner cases such as overflow, rounding boundaries, denormal handling, and exception conditions across all supported data types.
• Collaborate with physical design on floorplanning, placement, and routing of datapath structures, applying your understanding of layout implications to guide implementation decisions.

What you will bring

Must-haves

• 5 to 8 years of experience in datapath, execution unit, or high-performance logic design with shipped high-frequency products.
• Deep knowledge of computer arithmetic: adder architectures, multiplier structures, division algorithms, shifters, and their timing, power, and area tradeoffs.
• Expert timing intuition with a proven ability to write RTL that closes timing on aggressive cycle-time targets.
• Understanding of how datapath choices affect power and area, with real experience optimizing across all three dimensions simultaneously.
• Strong verification discipline for arithmetic corner cases, exception behavior, and wide-datapath debug.
• Familiarity with synthesis and physical design flows as they apply to datapath-heavy blocks, including datapath placement techniques.
• Persistence and creativity in squeezing the last picoseconds from critical paths without compromising correctness or robustness.

Nice-to-haves

• Experience with floating-point unit design and IEEE 754 compliance requirements.
• Knowledge of custom circuit design or standard-cell optimization for critical datapaths.
• Background in vector or SIMD datapath design with wide execution structures.
• Familiarity with formal verification techniques for arithmetic correctness.