Data Converter (ADC/DAC) Mixed Signal Engineer

Mixed Signal Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. Cadence Virtuoso, Spectre, Verilog-AMS, MATLAB behavioral modeling, Calibre, Python, SAR/pipeline/delta-sigma design flows

About the role

You will design data converters at a fabless semiconductor company where the ADC and DAC are the product differentiators. The team owns the full converter chain: architecture selection, transistor-level design, calibration, and silicon validation against ENOB, SFDR, and SNR targets. This role matters because converter performance is the headline datasheet number customers compare, and your design decisions set it. You will collaborate with digital designers on calibration logic and with test engineers on characterization, owning the converter's measured performance end to end.

What you will achieve

Ship one to two tapeout-ready converters per year (SAR, pipeline, or delta-sigma ADC; current-steering or resistor-string DAC) with silicon-measured ENOB and SFDR meeting the datasheet spec with margin.
Drive converter figure of merit by optimizing the power-noise-speed tradeoff: deliver designs that beat the prior generation's Schreier or Walden FoM by at least 20%.
Reduce calibration burden through circuit technique: choose architectures and matching strategies (dynamic element matching, chopping, background calibration) that relax post-silicon trim requirements.
Own converter behavioral modeling in MATLAB or Python: architecture exploration, noise and distortion budgeting, and Monte Carlo of mismatch effects that predict silicon within 3 dB of measured SNR.
Cut bring-up time by writing your own converter test plans: code-density histograms for INL/DNL, FFT-based SNR/SFDR measurement, and automated lab scripts that run the full characterization suite.

What you will bring

Must-haves

2-5 years designing data converters (ADC, DAC, or both) in CMOS with at least one tapeout and measured silicon results.
Deep understanding of converter architectures: SAR, pipeline, delta-sigma, flash, and current-steering or R-2R DACs, including their error mechanisms.
Fluency in the metrics that matter: ENOB, SNR, SFDR, THD, INL/DNL, and how each maps to circuit-level choices (capacitor sizing, amplifier gain, reference settling).
Strong behavioral modeling skills in MATLAB or Python for architecture selection and error budgeting before transistor design begins.
Experience with calibration techniques: foreground/background calibration, dynamic element matching, or digital error correction.
Lab measurement skills for converters: spectrum analysis, coherent sampling, and code-density testing.

Nice-to-haves

Experience with time-interleaved ADCs and skew/offset/gain mismatch calibration.
Knowledge of high-speed DAC design (current-steering, segmentation, dynamic performance).
Familiarity with on-chip reference and clock generation for converters.