Custom Silicon Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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To generate precise rejection-prevention feedback and application strategy, tell us where you're targeting.

NVIDIA

Qualcomm

AMD

Broadcom

Synopsys

Cadence

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The job description

Tech stack. SystemVerilog/UVM, first-silicon verification strategy, full-custom digital flows, signoff rigor, customer-spec compliance, rapid debug

About the role

You will verify bespoke, full-custom silicon programs at a semiconductor company where each chip is designed for one customer and one application, and there is no second spin in the budget. Working directly with the design team and often with the customer's engineers, you will prove the chip meets its exact specification the first time. Your verification discipline is what makes first-silicon success possible on programs with no margin for error, and your evidence package is what the customer stakes their product on. There is no merchant market to absorb a respin and no second customer to share the cost, so your thoroughness is the program's insurance policy.

What you will achieve

Deliver a first-silicon verification plan that maps every customer requirement to tests and coverage, with no requirement left unverified at tapeout.
Drive the design to zero known bugs at tapeout through exhaustive corner-case testing of the custom features that differentiate this chip.
Ship customer-facing verification evidence (coverage reports, compliance results, test summaries) that gives the customer confidence to commit their product to production.
Cut schedule risk by front-loading verification: testbench and checker development tracks RTL development week by week, never lagging it.
Reduce respin probability by running adversarial, out-of-spec stimulus on every custom interface, finding the failures a friendly testbench would miss.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience with at least one tapeout carried through to production or customer delivery.
Strong SystemVerilog/UVM skills with a bias toward thoroughness: you verify what the spec implies, not just what it states.
Experience with customer-driven or application-specific requirements and the discipline of requirements traceability.
Excellent debug skills under schedule pressure, with clear communication to designers and stakeholders about risk and status.
Understanding of full-chip concerns on custom programs: unique interfaces, analog and mixed-signal boundaries, package and board interactions.
Ownership mindset: you treat the chip's success as personal, because on custom silicon it is.
Professional maturity for customer interaction: you present verification status honestly and handle hard questions without spinning.

Nice-to-haves

Experience with mixed-signal verification or analog/digital co-simulation.
Familiarity with automotive, aerospace, or other high-reliability qualification flows.
Knowledge of DFT and manufacturing test as they constrain verification.
Exposure to contract or statement-of-work driven program management.