CPU Implementation Engineer

About the role

You will drive CPU blocks through the complete implementation flow at a semiconductor company, owning the path from RTL to tapeout-ready layout. Implementation engineers bridge front-end design and backend physical design: they run logic synthesis, develop and manage timing constraints, close timing across corners, integrate DFT structures, and ensure low-power design intent is correctly realized at every stage. You will develop the broad implementation expertise that turns good RTL into shippable, manufacturable silicon on aggressive schedules.

What you will achieve

• Own logic synthesis and timing constraints for CPU blocks, producing high-quality netlists with SDC constraints that accurately capture clocking, IO timing, and exception requirements.
• Drive block-level timing closure through the backend flow, resolving setup, hold, and transition violations systematically and coordinating with designers and physical design engineers on fixes.
• Integrate DFT structures including scan chains, memory BIST controllers, and boundary scan logic, ensuring full testability without compromising timing closure or area budgets.
• Implement low-power design intent through the flow including power gating controls, isolation cells, and retention registers, verifying correct realization with dedicated low-power checks at each stage.
• Run and resolve physical verification and equivalence checks including formal RTL-to-netlist equivalence, low-power verification, and constraint consistency analysis.
• Support hierarchical top-level integration and tapeout activities, ensuring your blocks meet every sign-off criterion including timing, power, physical verification, and DFT coverage on schedule.

What you will bring

Must-haves

• 2 to 5 years of experience in ASIC implementation including logic synthesis, static timing analysis, and backend flow exposure with tapeout experience.
• Strong understanding of timing constraints methodology: clock definitions, generated clocks, input and output delays, timing exceptions, and the discipline to write correct, maintainable SDC.
• Familiarity with DFT concepts including scan insertion, scan compression, ATPG, and memory BIST integration.
• Knowledge of low-power implementation flows, power intent formats, and power-aware verification checks.
• Scripting skills in TCL and Python for flow automation, report analysis, and regression management.
• Systematic problem-solving ability for the multi-variable optimization that implementation requires, balancing timing, power, area, and schedule simultaneously.
• Ownership and communication skills for coordinating effectively across design, DFT, and physical design teams with competing priorities.

Nice-to-haves

• Experience with advanced process node implementation challenges and variation-aware closure.
• Familiarity with formal equivalence checking methodologies and debug.
• Knowledge of physical design fundamentals including floorplanning, placement, and clock tree synthesis.
• Exposure to hierarchical implementation methodologies for large CPU blocks.