CPU Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

1 Which company are you aiming at?

To generate precise rejection-prevention feedback and application strategy, tell us where you're targeting.

NVIDIA

Qualcomm

AMD

Broadcom

Synopsys

Cadence

2 Send your application

You need an account so we know where to send the feedback.

Create an account Sign in

The job description

Tech stack. SystemVerilog/UVM, RISC-V or ARM ISA, instruction-level random testing, processor trace, coherency verification, pipeline microarchitecture

About the role

You will verify processor cores at a semiconductor company where the CPU is the heart of the product and every bug is architectural. Working directly with CPU microarchitects and RTL designers, you will prove that the pipeline executes the ISA correctly: branches predict, exceptions trap, memory orders, and speculation never corrupts state. Your checkers decide whether the core is trustworthy, your signoff gates tapeout, and your partnership with the microarchitects starts before the RTL exists. A single architectural bug in your core can invalidate the entire chip, which is why your verification is held to the highest standard in the company.

What you will achieve

Deliver a constrained-random instruction test environment that achieves full ISA coverage, including privileged modes, exceptions, and interrupts, before each milestone.
Drive pipeline corner-case coverage (hazards, flushes, mis-speculation recovery, multi-issue interactions) to closure, with the coverage model reviewed by designers.
Ship an independent instruction-level reference model or checker that catches any divergence between the DUT and the ISA specification, with zero false positives tolerated.
Cut debug time on processor failures by building trace-based triage that reconstructs the failing instruction stream and pinpoints the microarchitectural cause.
Reduce escape risk by co-reviewing microarchitecture changes with designers and updating verification plans before the RTL lands, not after.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience, with at least some exposure to processor or complex datapath verification.
Strong SystemVerilog/UVM skills and the ability to build self-checking environments for complex control logic.
Solid understanding of processor microarchitecture: pipelining, branch prediction, caches, virtual memory, and exception handling.
Knowledge of an industry ISA (RISC-V, ARM, or x86) including privileged architecture and memory ordering rules.
Experience with random instruction generators or established processor verification methodologies.
Ability to partner with microarchitects: reading pipeline diagrams and asking the questions that expose verification gaps early.
Obsession with correctness over coverage numbers: you hunt the bug the metrics say should not exist.

Nice-to-haves

Experience with formal verification of processor control logic or ISA compliance suites.
Familiarity with cache coherency protocols (MESI/MOESI) or memory consistency verification.
Knowledge of performance verification or power-aware techniques for CPUs.
Exposure to security verification for processors (speculative execution mitigations, privilege isolation).