CPU Cache Design Engineer

About the role

You will design CPU cache controllers and hierarchies at a semiconductor company, implementing the tag arrays, data arrays, replacement logic, and coherency engines that keep the processor fed with data. Cache designers work on some of the most concurrency-intensive logic in the chip: multiple outstanding requestors, in-flight transactions, snoop handling, and race conditions that must resolve correctly under every possible interleaving. Your designs must be simultaneously high-performance, area-efficient, and provably correct, since a cache bug can corrupt data silently.

What you will achieve

• Design cache controllers for L1, L2, or last-level caches including tag and data pipelines, miss status handling registers, fill and eviction logic, and snoop response paths.
• Implement coherency protocol engines supporting the program's chosen protocol, handling all transient states, race conditions, and deadlock scenarios with rigorous attention to correctness.
• Optimize cache access latency and throughput through pipeline design, banking strategies, and arbitration policies, meeting the aggressive timing targets these latency-critical structures demand.
• Integrate SRAM macros including redundancy and repair schemes, ECC protection, and timing closure of array interfaces in partnership with memory compiler and physical design teams.
• Drive verification of your cache designs to the quality required for first-silicon success, with coverage models that genuinely reflect protocol behavior, concurrency corner cases, and error scenarios.
• Support post-silicon validation of cache performance and correctness, diagnosing subtle coherency or performance anomalies with systematic measurement and analysis.

What you will bring

Must-haves

• 5 to 8 years of experience in cache, memory subsystem, or high-performance control logic design with shipped silicon.
• Deep understanding of cache organization, coherency protocols such as MESI variants, and the concurrency challenges inherent in cache controller design.
• Strong SystemVerilog design skills with demonstrated experience on complex, timing-critical control logic.
• Knowledge of SRAM characteristics including access timing, power behavior, ECC, and redundancy, and how they constrain controller design.
• Rigorous verification mindset appropriate for logic where a single escaped bug can cause silent data corruption in customer systems.
• Timing closure experience on high-frequency cache pipelines with tight array-interface budgets.
• Patience and precision for the detailed protocol work this domain demands, combined with the paranoia that keeps products correct.

Nice-to-haves

• Experience with formal verification of coherency protocols or cache controllers.
• Familiarity with advanced cache features such as way partitioning, QoS enforcement, or data compression.
• Knowledge of multi-level cache hierarchy performance tuning and modeling.
• Exposure to security aspects of caches including side-channel attack mitigations.