CMOS Mixed Signal Design Engineer

Mixed Signal Design Engineer Mid-level (L4 equivalent) 2-5 years

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Texas Instruments

Analog Devices

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Marvell

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The job description

Tech stack. Cadence Virtuoso, Spectre, Calibre, TCAD basics, PDK device characterization, MATLAB, bulk and finFET CMOS PDKs

About the role

You will be the CMOS device and process specialist on the analog team at a fabless semiconductor company, designing mixed-signal circuits with unusual depth in how the process itself behaves. The team relies on you for device selection, process-option tradeoffs, and the layout-dependent effects that make or break precision analog in modern CMOS. This role matters because in advanced CMOS the process is part of the circuit, and your understanding of it is a competitive advantage. You will be the team's first call on process questions, and your device characterization data will feed directly into design rules and sign-off criteria.

What you will achieve

Ship precision mixed-signal blocks (references, amplifiers, data converters) that exploit CMOS process options: deep n-well isolation, MIM/MOM capacitor choices, and resistor options selected for the best noise, matching, and drift.
Drive matching-limited performance by owning device-level characterization: measuring and modeling mismatch (Pelgrom coefficients), flicker noise, and temperature coefficients, then feeding them into design rules the team follows.
Reduce layout-dependent-effect surprises by characterizing WPE, LOD, STI stress, and well proximity on your blocks and building layout guidelines that keep post-silicon drift within budget.
Own the PDK relationship for the analog team: evaluating new process options, flagging model inaccuracies against silicon data, and working with the foundry to resolve device model issues.
Cut noise-limited failures by applying device-physics-driven design: flicker noise corners, thermal noise budgeting, and chopping or auto-zero techniques grounded in measured device data.

What you will bring

Must-haves

2-5 years designing analog/mixed-signal circuits in CMOS with unusual depth in device physics and process technology.
Strong understanding of CMOS device behavior: short-channel effects, mismatch mechanisms, flicker and thermal noise, and temperature dependence.
Experience characterizing devices: test structure design, measurement, and extraction of mismatch and noise parameters.
Knowledge of layout-dependent effects (WPE, LOD, STI stress, well proximity) and practical layout techniques to mitigate them.
Fluency in Spectre corners, Monte Carlo, and mismatch analysis with an eye on model accuracy versus silicon.
At least one tapeout where device or process choices you made measurably improved the silicon result.

Nice-to-haves

TCAD experience for device-level investigation.
Experience across multiple CMOS nodes or foundries, comparing process options.
Familiarity with FD-SOI specifics (back biasing, body effect control) if applicable.