CMOS IC Design Engineer

Analog IC Design Engineer Mid-level (L4 equivalent) 2-5 years

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Skyworks

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The job description

Tech stack. Deep-submicron CMOS, short-channel effects, low-voltage design, device modeling (BSIM/PSP), Cadence Virtuoso, Spectre, DFM-aware design

About the role

You will join a fabless semiconductor company as a CMOS-focused analog IC design engineer, working in advanced planar and FinFET processes where device behavior diverges sharply from long-channel theory. The team tapes out in modern nodes where every circuit must respect short-channel effects, low supplies, and dense DFM rules. This role matters because extracting analog performance from digital-optimized CMOS is a specialized skill: your process fluency is what lets the products hit their specs in nodes built for logic. Each new node changes the analog rules again, so deep process fluency never goes stale here.

What you will achieve

Ship analog blocks in deep-submicron CMOS that meet gain, noise, and linearity targets despite low headroom and short-channel effects
Design low-voltage topologies (folded, inverter-based, bulk-driven) that squeeze performance from sub-1V supplies
Cut DFM and lithography risk by designing with process constraints in mind, achieving clean tapeout signoff without layout-driven redesigns
Drive model-to-silicon correlation for short-channel devices, feeding back discrepancies that improve the PDK for future designs
Deliver variation-tolerant designs using mismatch-aware sizing and calibration that hold yield in high-volume manufacturing
Support node migration of proven blocks, re-centering designs for new device characteristics without full redesigns
Evaluate new PDK releases and device options, advising the team on which structures to adopt or avoid

What you will bring

Must-haves

2-5 years designing analog circuits in deep-submicron CMOS (65nm or below) with shipped silicon
Strong understanding of short-channel effects: velocity saturation, DIBL, gate leakage, and their impact on analog design choices
Experience designing at low supply voltages, with techniques for maintaining gain and swing under headroom constraints
Fluency in Cadence Virtuoso and Spectre, including the model options and simulation care advanced nodes require
Working knowledge of DFM rules, density requirements, and antenna rules that constrain analog layout in modern processes
Solid grasp of mismatch and variability: Pelgrom modeling, layout techniques, and statistical design
B.S. or M.S. in Electrical Engineering with a device physics or analog circuits emphasis

Nice-to-haves

FinFET-specific design experience and understanding of quantized device sizing
Familiarity with EM/IR analysis for supply networks in dense analog blocks
Prior node-migration or IP-porting work across foundries