Chief ASIC Verification Engineer

ASIC Verification Engineer Chief, company-wide technical authority 15+ years

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The job description

Tech stack. Verification strategy, UVM, formal verification, emulation strategy, EDA partnerships, coverage-driven methodology, executive technical leadership

About the role

You will be the company-wide technical authority for verification at a semiconductor company shipping multiple product lines across advanced nodes. The chief verification engineer sets the verification vision for the entire company: the methodology every project follows, the signoff standards executives rely on, the technology bets that determine competitiveness five years out. Architects, vice presidents, and the CEO consult your judgment on tapeout risk, and your standards define what quality means across the organization. You will make the hard calls: which technologies to bet on, which projects need intervention, and when a tapeout is truly ready. The verification culture of the company, its quality record, and its ability to scale all trace back to the direction you set.

What you will achieve

Set the company-wide verification strategy and signoff standards, unifying methodology across all product lines and design centers.
Reduce verification-driven schedule slips across the portfolio by 30 percent through stronger planning discipline, reuse strategy, and risk-based verification investment.
Drive the multi-year verification technology roadmap: formal adoption, emulation strategy, AI-assisted verification, and EDA vendor partnerships.
Serve as the final technical authority on tapeout readiness, with risk assessments that executives trust for go/no-go decisions on flagship products.
Build the company's verification leadership bench by mentoring principal and staff engineers and shaping the hiring bar for the entire verification organization.

What you will bring

Must-haves

15 or more years of ASIC verification experience with leadership across multiple successful tapeouts at advanced nodes.
Demonstrated company-wide or multi-business-unit influence on verification methodology and quality standards.
Deep expertise spanning simulation, formal verification, emulation, and post-silicon, with judgment on how they combine into a signoff strategy.
Track record of setting technical direction that multiple organizations successfully executed.
Executive communication skills: presenting tapeout risk, technology investment, and quality trade-offs to C-level leadership.
EDA industry relationships and experience driving vendor roadmaps through partnership and evaluation.
History of building and mentoring senior technical leaders across the verification discipline.

Nice-to-haves

Industry recognition: keynote talks, standards committee participation, or widely adopted methodology publications.
Experience with functional safety (ISO 26262) or other regulated verification regimes at organizational scale.
Background in founding or scaling verification organizations through rapid company growth.
Experience advising EDA startups or serving on technical advisory boards.