Advanced Node Semiconductor Engineer

About the role

A semiconductor manufacturer developing sub-5nm technologies needs an engineer focused on advanced-node integration and device challenges, where every nanometer of margin has already been spent. You will work on FinFET and gate-all-around structures, EUV patterning interactions, and design-technology co-optimization, solving problems that did not exist at the previous node. This is where Moore's law gets its next chapter, and the solutions you develop become the design rules the industry builds on. The engineer also leads the DTCO working groups where design and technology teams negotiate the rules together, since sub-5nm success requires co-optimization, not handoffs.

What you will achieve

• Deliver integration solutions for GAA or advanced FinFET modules that meet performance and leakage targets on first silicon, through rigorous interface design and pre-silicon risk analysis.
• Drive variability reduction so within-die and die-to-die variation stay within DTCO-assumed budgets, protecting the power-performance-area commitments made to product teams.
• Reduce EUV-related stochastic defectivity by 30 percent through process and design-rule co-optimization, attacking a failure mode that does not scale with traditional process control.
• Own advanced-node test-chip analysis, extracting learning that feeds directly into the next node definition rather than sitting in reports nobody reads, and reviewed with the node architecture team within 2 weeks of data availability.
• Cut node development cycle time by accelerating learning cycles between design, process, and metrology teams, so each silicon loop teaches more than the last, compressing the learning that traditionally took multiple node generations.

What you will bring

Must-haves

• BS or MS in electrical engineering, physics, or materials science, with an advanced degree preferred for this depth of technical work.
• 2 to 5 years in advanced-node development, integration, or device engineering, with 7nm or below experience preferred.
• Understanding of FinFET or GAA device physics and the process challenges unique to 3D transistor architectures.
• Experience with EUV lithography interactions and multi-patterning schemes, including stochastic effects and their mitigation.
• Familiarity with DTCO concepts and standard-cell-level process feedback, speaking the language of both designers and process engineers.
• Strong collaboration skills across design, process, and EDA teams, building alignment when each group sees the problem differently.

Nice-to-haves

• Backside power delivery or 3D stacking experience for next-generation integration schemes.
• Knowledge of high-NA EUV requirements and their process implications.
• Experience with advanced-node PDK development or model-hardware correlation.