Advanced Node IC Design Engineer

Analog IC Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. FinFET and GAA devices, 5nm/3nm processes, EM/IR analysis, layout-dependent effects, DFM, Cadence Virtuoso, Spectre, advanced PDK flows

About the role

You will join a fabless semiconductor company designing analog and mixed-signal circuits in the most advanced process nodes in production. The team works at 5nm, 3nm, and beyond, where quantized devices, layout-dependent effects, and ultra-low supplies rewrite the analog playbook. This role matters because the company's flagship digital products need analog that survives in nodes built for logic: your circuits make the advanced-node SoC actually work. The node roadmap never pauses, and this team is always first to face what the new physics demands. You will also build the layout-dependent-effect modeling checklist the team applies to every tapeout, capturing well-proximity and stress effects before they become silicon surprises.

What you will achieve

Ship analog blocks in FinFET and GAA nodes that meet performance targets despite quantized sizing and sub-0.8V supplies
Design with layout-dependent effects (WPE, LOD, PSE) as first-class variables, centering circuits against effects older nodes never had
Cut EM/IR risk through rigorous power-grid analysis and current-density-aware routing in dense analog blocks
Drive DFM-clean tapeouts in nodes where double patterning and restrictive design rules punish careless layout
Deliver variation-tolerant designs using statistical methods suited to advanced-node variability, holding yield at high volume
Own node-specific model correlation, feeding back device behavior the PDK misses to improve future design cycles
Partner with foundry teams on early PDK access, influencing device offerings to better serve analog needs

What you will bring

Must-haves

2-5 years designing analog or mixed-signal circuits in FinFET nodes (16nm/7nm/5nm or below) with shipped silicon
Strong understanding of FinFET and GAA device behavior: quantized widths, self-heating, and layout-dependent effects
Experience designing at ultra-low supplies with techniques for gain, swing, and linearity under severe headroom limits
Proficiency in Cadence Virtuoso and Spectre within advanced-node PDK flows, including reliability and aging analyses
Working knowledge of EM/IR signoff for analog blocks and the routing discipline it requires
Familiarity with restrictive DFM rules: coloring, density, and cut-mask constraints that shape analog layout
B.S. or M.S. in Electrical Engineering with a semiconductor devices or analog circuits emphasis

Nice-to-haves

Experience with backside power delivery or buried power rail implications for analog
Familiarity with cryogenic or extreme-environment operation of advanced-node devices
Prior work porting analog IP across advanced nodes (e.g., 7nm to 5nm to 3nm)