Advanced Node CPU Design Engineer

About the role

You will design CPU logic for the most advanced process nodes at a semiconductor company, where shrinking geometries bring formidable new challenges alongside their benefits. Advanced-node designers face increased process variation, tighter electromigration limits, complex multi-patterning design rules, and power densities that demand fundamentally new techniques. You will combine strong design fundamentals with node-specific expertise, adapting RTL practices, timing strategies, and power approaches to extract the technology's advantages while managing its risks, on some of the first CPUs ever built in the node.

What you will achieve

• Design CPU blocks optimized for advanced process nodes, applying variation-aware RTL practices, robust clocking and reset strategies, and margin policies appropriate to the technology's characteristics.
• Address electromigration and IR drop challenges proactively in logic design, understanding current density implications and collaborating with physical design on robust power grid implementation.
• Adapt timing closure strategies to advanced-node realities including heightened variation, complex multi-corner scenarios, and aging effects, achieving predictable, repeatable results.
• Implement aggressive low-power techniques suited to the node's power profile, whether leakage-dominated or power-density-limited, balancing active and leakage power for the product's actual use cases.
• Resolve node-specific design rule, lithography, and manufacturability issues in your blocks, working closely with process integration and physical design teams on clean, yield-friendly logic.
• Contribute to the organization's advanced-node design guidelines, capturing hard-won lessons from first silicon into practices, checklists, and training that de-risk subsequent programs.

What you will bring

Must-haves

• 5 to 8 years of experience in digital design with at least one advanced-node tapeout at 7nm or below, or equivalent FinFET process experience.
• Strong SystemVerilog design skills with clear understanding of how RTL choices interact with advanced-node physical effects.
• Knowledge of process variation, transistor aging, electromigration, IR drop, and other deep-submicron challenges and their concrete design implications.
• Experience with low-power design techniques and power intent flows including UPF-based implementation.
• Timing closure experience spanning multi-corner, multi-mode analysis and variation-aware methodologies such as AOCV or POCV.
• Ability to collaborate effectively with process, device, and physical design teams on node-specific issues, speaking enough of their language to be productive.
• Adaptability and learning speed, since each new node brings unique characteristics that invalidate some prior assumptions.

Nice-to-haves

• Experience with gate-all-around transistors or other next-generation device architectures.
• Knowledge of 3D integration, chiplets, or advanced packaging implications for logic design.
• Familiarity with design-technology co-optimization practices and early node enablement.
• Background in high-performance CPU blocks where node challenges are most acute.